Fin Field Effect Transistors (FinFETs) have attracted much attention due to their excellent performance in suppressing the short channel effects. FIG. 1 shows a perspective view of an existing FinFET device. As shown in FIG. 1, the FinFET comprises: a bulk-Si semiconductor substrate 100; a fin 101 formed on the bulk-Si semiconductor substrate 100; and a gate stack 102 astride the fin 101. The gate stack 102 comprises a gate dielectric layer, a gate electrode layer (not shown), and an isolation layer (e.g. SiO2) 103, for example. In the FinFET, under the control of the gate electrode, conductive channels are created in the fin, specifically, in three surfaces (a left side surface, a right side surface, and a top surface in the figure) of the fin 101. In other words, the portions of the fin 101 under the gate electrode serve as a channel region. A source region and a drain region are located at opposing sides of the channel region.
In the example shown in FIG. 1, the FinFET is formed on the bulk-Si semiconductor substrate. However, the FinFET can also be formed on other types of substrate, such as a Silicon-on-Insulator (SOI) substrate. Furthermore, the FinFET shown in FIG. 1 is called a tri-gate FET, because the channel are formed in three surfaces of the fin 101. Alternatively, a double-gate FET may be formed by arranging an isolation layer (e.g. a nitride layer, etc.) between the top surface of the fin 101 and the gate stack 102. In such a case, the top surface of the fin 101 is not controlled by the gate electrode, and therefore no channel will be created therein.
Although the FinFET provides improved performances in comparison with conventional Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), it also brings some design challenges. In particular, there are generally no limitations on the device widths for the conventional MOSFETs, but the fins of the FinFETs typically need to be of the same height. This is because the fins in different FinFETs need to have the same physical width in order to ease lithographic patterning of the fins.
In other words, the conventional MOSFET has two parameters, i.e. a channel width W and a channel length L, for controlling the on current and the cutoff current of the transistor. However, the FinFET only has one parameter, the length L of the Fin, for controlling the on current and the cutoff current of the transistor. This is because the fin has a fixed height and therefore the channel width is fixed. As a result, for a given length L of the transistor, which defines a ratio between the on current and the cutoff current, the on current amount from one fin is fixed.
However, high-performance integrated circuits usually need transistors with varied on currents. One way to vary the on currents is to change driving abilities of respective devices by varying their fin heights. Layout area will not increase because only vertical dimensions are changed.
However, there has not been any effective way to change the fin heights. Therefore, a new semiconductor manufacturing process is needed for integrating a plurality of semiconductor devices with different device dimensions or fin heights on a single wafer.